With the rapid development of semiconductor manufacturing technology, semiconductor devices have been developed toward with higher component density and higher integration degree. Transistors, as the most basic semiconductor devices, have been widely used. With the increasing of the component density and the integration degree of the semiconductor devices, dimensions of a transistor are scaled down.
The transistor includes: a substrate; a gate structure on the substrate; a sidewall spacer on a sidewall of the gate structure; a source and drain doped region in the substrate on both sides of the sidewall spacer; a dielectric layer on the gate structure and the source and drain doped region; and a source-drain plug in the dielectric layer. The source-drain plug is connected to the source and drain doped region. The source-drain plug, the gate structure and the sidewall spacer between the source-drain plug and the gate structure form a capacitor. If a capacitance value of the capacitor is large, a parasitic capacitance of the transistor is large, a RC (resistor-capacitor) delay effect of the transistor is likely to increase, and the performance of the semiconductor structure is degraded.
However, the parasitic capacitance of conventionally-formed semiconductor structures is large, and the performance of the semiconductor structure is poor and still needs to be improved. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.